1. Field of the Invention
The invention relates to MOS circuits and more specifically to complementary MOS voltage level shift circuits.
2. Description of the Prior Art
There are several areas, for example in MNOS memories, where a high-speed, high-voltage buffer is required. One form of such buffer incorporates all P-channel devices and has undesirable high power dissipation. In addition, since these P-channel devices dissipate so much power, they have to have small width-to-length ratios. Such devices have slower switching speeds. N-channel devices are not normally used, for example, in MNOS memories because their reverse breakdown characteristics are such that voltage swings are limited to about 15 V. Usually, a 30 V swing is required to obtain good writing characteristics in MNOS memories. Another type of buffer uses multiple clocking inputs which complicates timing considerations.
What is needed, then, is a simple, high speed, high voltage MOS memory buffer which dissipates a minimal amount of power, and whose voltage output is capable of making large swings, for example, 30 V.